This article reflects the opinion and analysis as well as information collated by AE Research Management Sdn Bhd, and does not constitute an investment advice or recommendation
Semiconductor Technology Roadmap
During the mid-1980s, semiconductor node (traditionally defined as half the separation between two metal lines) was 1000 nm. For every subsequent 1.5 years or so, the node will shrink with the adoption of more advanced fabrication process – using shorter wavelength lithography light sources, higher numerical aperture chamber in which the process takes place, and multiple-patterning techniques. By the late 2010s, the most advanced nodes have shrunk to mere 7-10nm!
The node shrink allows semiconductor makers to pack in more bits & transistors into the same silicon area (ie increased density), reduce power consumption and boost the speed of the IC (integrated circuit). In parallel is the lowering of the unit cost of memory & logic.
In the next 5 years, however, the industry will face scientific limitations with profound implications.
Semiconductor memories is currently approaching such limit at 1Z nm (~10nm). Existing memory structure is based on 1 transistor + 1 capacitor cell. There is a physical limit to the pitch (size) of the capacitor cell, in that it must be able to hold a minimum number of electrons to store data. Generally, it will not be feasible to shrink the node below 10 nm, otherwise there is unacceptable risk of data error if all electrons escape from a cell.
Chart 1: Sharp deceleration in DRAM memory bit density
With scaling levelling off at around 10 nm, the 20-30% p.a. rise in DRAM bit density that the industry has been accustomed to, will grind to a halt (see chart 1). There will be some process refinements to secure bit density growth by fabricating very tall (and thin) capacitance cell, ie high aspect ratio structures. But such structures are difficult to fabricate, requiring expensive and slow molecular-level etch & deposition processes. Even then, these refinements could only squeeze out about 5% p.a. in additional bit density, not much more.
Therefore, in order to meet explosive demand for data processing & storage in the Internet-of-Things (IOT)/5G era, much more semiconductor wafer area will be required since density cannot be boosted further. There will be acceleration in demand for high-specifications silicon wafers – with perfect crystal structure, ultra-purity et al – used at the 10 nm nodes, which can only be reliably supplied by two companies.
On the losing side, stagnation of the process roadmap will give opportunity for budding Chinese memory makers to close the technological gap and challenge the dominance of Samsung Electronics, Hynix and Micron, even at the leading-edge. By some estimates, Chinese memory makers are expected to commence commercial production this year (2020) with market share of about 5%!
For logic chips, scaling is still possible with current visibility to 3-5 nm (chart below), through the use of the shorter wavelength EUV (extreme ultra violet) optical lithography and adoption of ever more complex 3-D transistor structures such as the GAA FET (gate-all-round field effect transistor).
Chart 2: Process technology roadmap for Logic
Nonetheless, there are still major technical limits on two fronts that will tend to result in higher wafer area usage than otherwise.
For logic chips in PCs/notebooks, the Intel X86 CPU architecture poses a serious current leakage issue as it approaches the clock speed of 5GHz. Instead of fabricating all the CPU functional blocks into a single die at ever smaller nodes, logic chipmakers are now adopting chiplets architecture – separate small semiconductors for each of the various CPU functions, and connecting them in a package instead.
Then, there is the miniaturization limit posed by the phenomena of ‘dark silicon’. Essentially, when transistor gate density increases, heat become a major problem if the entire surface of a sub10nm semiconductor is powered-on simultaneously – the heat intensity can approach that of a jet engine! Any solution will necessitate additional control circuitries or wafer area redundancies, all of which tend to boost the demand for silicon wafer area.
Advanced silicon wafers and molecular-level etch/deposition system
In summary, the various scientific limits that the semiconductor process roadmap will face in coming years, will result in accelerating demand for high-specification silicon wafers and for advanced molecular-level etching/deposition systems.